GoBright Group
Shenzhen Gobright TECH CO.,Ltd

Block #5, the 4th Industry Park of Shuitian, Shiyan Town, Baoan Zone, Shenzhen, Guangdong, 518000, China.
Telephone: +86 755 86327335
Fax: +86 755 26901907
Mob: +8615889758291
QQ: 703118636
Skype: eric-gobright
Wechat: 369280335
Whatsapp: +8615889758291
CPU-monitoring Loop Eyes System Power
Updated: 2013-12-11 15:03:13     (GOBRIGHT NEWS DEPT)

Source: GoBright
Traditional approaches to portable power management have focused solely on power delivery. But with the efficiencies of  power-management ICs reaching 95 percent, further improvements in battery life based on regulator efficiency can seem  minuscule.
A system-level approach to power management, however, demands industrywide collaboration and standardization. Such  collaboration does not come easy; it requires companies to change business models and reach out across the boundaries, even  if it means collaborating with competitors.
In November 2002, National Semiconductor and ARM Ltd. started an industrywide collaboration in power management by   announcing a relationship based on system-level energy-management solutions.
National unveiled a system-level energy-conservation solution called PowerWise technology, while ARM unveiled its Intelligent Energy Manager (IEM) technology,  designed to reduce power consumption for ARM-powered system-on-chip devices.
ARM's IEM reduces the performance level (frequency) of the processor without allowing applications to miss their  deadlines. (Completing a task before a deadline and then idling is significantly less energy-efficient than running the task  more slowly so that the deadline is met exactly.) Here, the primary challenge lies in predicting the right level of  performance for the application. The IEM software and hardware monitor the execution and communication characteristics of  workloads, predict the performance levels required and set the performance of the processor to the level that minimizes  energy use while still meeting the application deadlines.
The ARM core, for example, has four selectable performance levels, each corresponding to a clock frequency (300, 400, 500?? and 600 MHz). The more tasks you can perform with a slower clock, the more you conserve battery life-and IEM is good at  matching tasks to the lowest clock frequency.
National's PowerWise technology em-beds closed-loop systems in which the power-consuming and the -delivery systems operate  in close cooperation. Its goal is to cut the demands on the power source while providing peak energy efficiency. A top-down  energy-estimation approach calls for several classes of PowerWise monitors, each designed to control the consumption of  various subsystems of the mobile phone. Thus, the ARM-National Semiconductor partnership will introduce several devices and methodologies for mobile-phone embedded processors.
Processors are designed to operate reliably over a wide range of temperature levels and silicon process variations. Large safety margins are used to ensure a large safe-operating range at the cost of reduced power efficiency. Just as ARM IEM  performance-setting algorithms optimize power consumption based on workload variations, National's PowerWise devices ensure?? that the processor does not have to operate under worst-case assumptions, by tuning operating parameters based on temporal?? environmental conditions as well as to process-induced variations among devices.
The heart of the PowerWise technology for embedded processors (such as mobile-phone baseband or application processors) is  a 3,000-gate synthesizable digital core called the Adaptive Power Controller. The APC accurately monitors the power consumed?? by the processor and tracks the temperature and device-to-device process variations. The intelligence in the APC is  communicated to an external energy-management unit over the two-wire PowerWise Interface.
The APC works in a closed-loop system to reduce the supply voltage of the processor without sacrificing operational?? stability by monitoring the margin between expected and actual operating conditions. The APC also receives performance requests from ARM's IEM technology and provides closed-loop adaptive voltage scaling (AVS).
AVS is a new voltage-scaling approach that offers improved performance and ease of implementation over existing open-loop  dynamic voltage-scaling (DVS) schemes. Using the inherent characteristics of the APC, AVS scales the supply voltage to the absolute minimum required for any given device and for any operating condition, all without any processor intervention.
Existing proprietary open-loop DVS schemes allow the processor to set the supply voltage based on a lookup table of  voltage/frequency pairs. The table must be developed based on extensive device characterization to ensure adequate safety  margins for all operating conditions and process corners. The closed-loop AVS technology eliminates the need to maintain such  a table and the related characterization, as the APC compensates for process corners and variations in operating conditions.
In closed-loop AVS, the APC together with the PowerWise Interface-compliant energy-management unit provide the fastest  possible response time and coordinate all the clock-switching activities. When switching from a lower to a higher frequency, the APC inherently ensures that the supply voltage is high enough to support the new frequency. The synthesizable nature of  APC makes it process-independent and transportable.
Using AVS on an ARM7TDMI-S-based image processor results in more than 90 percent power savings. For a device from a typical   process corner lot operating at maximum frequency, AVS eliminates safety margins and reduces the power consumption by  approximately 35 percent over fixed-voltage or DVS schemes. Devices capable of operating at higher speeds will see even  greater benefits with AVS.